1. Field of the Invention
The present invention relates to a non-volatile semiconductor memory device and a method for manufacturing it, particularly to a non-volatile semiconductor memory device having a floating gate and a control gate which is formed to overlap the floating gate through a tunneling oxide film covering the floating gate, and a method of manufacturing it. More particularly, the invention relates to technology for preventing a reduction in the erasure efficiency when data erasure is repeated by extracting charges (electrons) stored in the floating gate towards the control gate, thereby extending the operation life (cycle life) of a memory cell.
2. Description of the Related Art
In an electrically erasable non-volatile semiconductor memory device composed of memory cells each consisting of a single transistor, particularly a programmable ROM (EEPROM: Electrically Erasable and Programmable ROM, also referred to as xe2x80x9cflash memoryxe2x80x9d), each memory cell consists of a transistor in a double-gate structure having a floating gate and a control gate. In such a memory cell transistor in a double gate structure, write of data is performed by accelerating hot electrons generated on the side of a drain region so as to be injected into the floating gate. Erasure of data is performed by extracting charges from the floating gate to the control gate through F-N tunneling (Fowler-Nordheim tunneling).
FIG. 9 is a plan view of a memory cell portion of a non-volatile semiconductor memory device having a floating gate. FIG. 10 is a sectional view taken across X1xe2x80x94X1 in FIG. 9. The memory cell portion adopts a split gate structure in which a control gate is arranged in parallel to a floating gate.
A plurality of element isolation films 2 of a thick LOCOS oxide film selectively formed by LOCOS (Local Oxidation Of Silicon are formed in stripes on a surface area of a P-type semiconductor substrate 1 so that element areas are sectioned from one another. Floating gates 4 are formed on the semiconductor substrate 1 so that each of them extends between adjacent element isolation films 2 through an oxide film 3A. The floating gate 4 is arranged individually in each memory cell. By selective oxidation, a selective oxide film 5 on the floating gate 4 is formed to be thicker in the central area and have an acute corner on the edge thereof so that concentration of an electric field is likely to occur at the edge of the floating gate 4 during data erasure.
On the semiconductor substrate 1 on which the plurality of floating gates 4 are arranged, control gates 6 are arranged so as to correspond to the respective columns of the floating gates 4 through the tunneling oxide film 3 integrated to the oxide films 3A. The control gate 6 partially overlaps the floating gate 4 and the remaining portion thereof abuts on the semiconductor substrate 1 through the oxide film 3A. The floating gates 4 and the control gates 6 are arranged so that they are symmetrical from each other in adjacent columns.
An N-type drain region 7 and a N-type source region 8 are formed in the substrate areas between the control gates 6 and between the floating gates 4. The drain region 7 is individually surrounded by the element isolation films 2 between the control gates 6, whereas the source region 8 extends along the control gate 6. These floating gate 4, control gate 6, drain region 7 and source region 8 constitute a memory cell transistor.
A metallic wiring 10 of aluminum alloy i s arranged on the control gate 6 in a direction perpendicular to the control gate through an interlayer insulating film 9. The metallic wiring 10 is connected to the drain region 8 through a contact hole 11. Each control gate 6 serves as a word line whereas the source region 8 extending along the control gate 6 serves as a source line. The metallic wiring 10 connected to the drain region 7 serves as a bit line.
In the case of the memory cell transistor in a double gate structure, the xe2x80x9conxe2x80x9d resistance between the source and drain varies according to the quantity of charges injected into the floating gate 4. Therefore, by selectively injecting the charges into the floating gate 4 so that the xe2x80x9conxe2x80x9d resistance of a specific memory cell transistor is varied, a difference thus produced in the operation characteristic of each memory cell transistor is correlated with the data to be stored.
The respective operations of write, erasure and read of data in the non-volatile semiconductor memory device can be performed in the following manner. In the write of data, the potential of the control gate 6 is set at 2 V; the potential of the drain region 7 is set at 0.5 V and the high potential of the source region 8 is set at 12 V. In this case, the potential of the floating gate 4 is elevated to about 9 V because of the difference in the capacitive couplings between the control gate 6 and floating gate 4 and between the floating gate 4 and substrate (source region 8) (i.e. capacitance between the control gate 6 and floating gate 4  less than capacitance between the floating gate 4 and substrate). Thus, the hot electrons generated in the vicinity of the drain region are accelerated toward the floating gate 4 and injected into the floating gate 4 through the oxide film 3A, thereby making the write of data.
In the erasure of data, the potential of each of the drain region 7 and source region 8 is set at 0 V and that of the control gate 6 is set at 14 V. In this case, the charges (electrons) pass through the tunnelling oxide film 3 from the acute portion at the corner of the floating gate 4 by the F-N (Fowler-Nordheim tunneling) conduction so that they are discharged into the control gate 6, thereby making the erasure of data.
In the read of data, the potential of the control gate 6 is set at 4 V; that of the drain region 7 is set at 2 V and that of the source region 8 is set at 0 V. In this case, if the charges (electrons) have been injected in the floating gate 4, the potential at the floating gate 4 becomes low. Therefore, no channel is formed beneath the floating gate 4 so that a drain current does not flow. In contrast, if the charges (electrons) have not been injected in the floating gate 4, the potential of the floating gate 4 becomes high. Therefore, the channel is formed beneath the floating gate 4 so that the drain current flows.
FIG. 7 is a graph showing a measurement result of a cycle life (number of times of the erasure/write of data: E/W Cycle) in a conventional device having the above configuration. As seen from the graph, the measured current in the memory cell (ordinate) lowers with an increase of the E/W cycle (abscissa). Incidentally, as seen, in the conventional non-volatile semiconductor memory device, the number of times of erasure/write of data when the cell current lowers to a decidable level (e.g. when the memory cell current of the memory cell in the erasure state becomes 30 xcexcm which is 30% of the initial value of 100 xcexcm) is 50,000 times (see dotted line in FIG. 7). A general programmable memory requires the E/W cycle of about 100,000 times, and that of 50,000 times is insufficient. Therefore, it has been demanded to increase the E/W cycle.
As a result of analysis by the inventors of the present invention, it h as been found that the material of the interlayer insulating film for med on the memory cell transistor is correlated with the cycle life.
Specifically, in an device configuration in which a relatively large level difference occurs because the control gate overlaps the floating gate like the non-volatile semiconductor memory device according to the present invention, an interlayer insulating film 9 subjected to an etch back step of an SOG (Spin on Glass) film is formed.
The inventors have supposed that the cycle life is influenced by the fact that moisture or H atoms (mainly moisture in the SOG film) contained in the TEOS film and SOG film will be diffused and trapped by the tunneling oxide film.
An object of the present invention is to provide a non-volatile semiconductor memory device capable of improving the operation life of a memory cell, and its manufacturing method.
In order to attain the above object, the invention is characterized by provision of a barrier film for preventing the moisture or H atoms in an interlayer insulating film from being diffused and an oxide film covering the barrier film formed by plasma CVD, which are formed between a metallic wiring and the interlayer insulating film.
Specifically, the non-volatile semiconductor device according to the invention is characterized, as shown in FIG. 5 in that a barrier film of a SiON film is formed below an interlayer insulating film which is a single layer film or laminated film of an TEOS film and SOG film covering a floating gate 4 and control gate 6. The SiON film which is good in moisture blocking but poor in coverage (particularly at the corner of the object to be covered) is covered with another TEOS film 19A which is better in coverage than the SiON film, thereby improving the barrier property of the barrier film. Such a configuration prevents moisture or H atoms (mainly moisture the SOG film) contained in the TEOS film and SOG film from being diffused and trapped by the tunneling oxide film 3, thereby improving the trap-up rate and hence endurance characteristic. This configuration prevents the moisture and H atoms from being diffused and trapped by the gate oxide film, thereby improving the hot carrier resistant characteristic.
The manufacturing method according to the invention is characterized by comprising the following steps. First, as shown in FIG. 1A, a conductive polysilicon (poly-Si) film is formed on a gate oxide film 3A which has been formed on a P-type Si substrate by thermal oxidation, and thereafter the polysilicon film is patterned to form a floating gate 4. Next, as shown in FIG. 1B, a tunneling oxide film 3 is formed to cover the floating gate 4, and on the tunneling oxide film 3, a conductive film 6A composed of a poly-Si film and tungsten silicide (WSix) film and an insulating film 9A are stacked and the stacked film is patterned to form a control gate 6 having a region overlapping the floating gate 4 through the tunneling film 3 (FIG. 2A). Subsequently, as shown in FIGS. 2B and 3A, source/drain regions 7 and 8 are formed on the surface layer of the substrate so that they are adjacent to the floating gate 4 and control gate 6, and thereafter, as shown in FIG. 3B, metallic wirings 10 are formed which are in contact with the control gate 6 and/or the source/drain regions 7 and 8 through the underlying insulating film 9. Further, a barrier film 20 of e.g. SiON film capable of preventing moisture and H atoms contained in the interlayer insulating film 19 from being diffused is formed below an upper insulating film 19 which is a single layer or laminate layer of e.g. TEOS film, SOG film, etc. formed so as to cover the upper layer of the memory cell portion consisting of the elements described above (FIG. 4A). Finally, as shown in FIG. 4B, a TEOS film 19A is formed to cover the barrier film 20 as shown in FIG. 4B, and the TEOS film is etched back so that it is not removed completely, thereby forming the interlayer insulating film 19 composed of the SOG film 19B and TEOS film 19C.
Another manufacturing method according to the invention is characterized by comprising the following steps. First, as shown in FIG. 6A, a gate oxide film 3A is formed by thermal oxidation of the surface of a P-type Si substrate, a polysilicon (poly-Si) film 4B made conductive is formed on the gate oxide film 3A, a silicon nitride film 53A having an opening with a prescribed pattern is formed on the poly-Si film 4B, and thereafter a selective oxide film 5 is formed by selective oxidation of the poly-Si film 4B through the opening 53A (FIG. 6A). Next, as shown in FIG. 6B, the poly-Si film 4B is etched using as a mask the selective oxide film 5 to form a floating gate 4 having an acute corner 4A on its upper portion. Subsequently, as shown in FIG. 6C, a tunneling oxide film 3 is formed to cover the floating gate 4, on the tunneling oxide film 3, a conductive film 6A composed of a poly-Si film and tungsten silicide (WSix) film and an insulating film 9A are stacked and thereafter the stacked film is patterned to form a control gate 6 having a region overlapping the floating gate 4 through the tunneling film 3. Subsequently, as shown in FIGS. 2B and 3A, source/drain regions 7 and 8 are formed on the surface layer of the substrate so that they are adjacent to the floating gate 4 and control gate 6, and thereafter, as shown in FIG. 3B, metallic wirings 10 are formed which are in contact with the control gate 6 and/or the source/drain regions 7 and 8 through the underlying insulating film 9. Further, a barrier film 20 of e.g. SiON film capable of preventing moisture and H atoms contained in the interlayer insulating film 19 from being diffused is formed below an upper insulating film 19 which is a single layer or laminate layer of e.g. TEOS film, SOG film, etc. formed so as to cover the upper layer of the memory cell section consisting of the elements described above (FIG. 4A), Finally, as shown in FIG. 4B, a TEOS film 19A is formed to cover the barrier film 20 as shown in FIG. 4B, and the TEOS film 19A is etched back so that it is not removed completely, thereby forming the interlayer insulating film 19 composed of the SOG film 19B and TEOS film 19C.
In accordance with the present invention, in the process of flattening the interlayer insulating film composed of an oxide film, SOG film, etc. which is formed by the plasma CVD on an SiON film serving as a barrier film formed so as to cover the memory cell portion, the oxide film is etched back by a degree not completely removed so that the barrier property of the SiON film can be improved. This is because the SiON film having inferior coverage is covered with the organic oxide film having better coverage than the SiON film.
Therefore, production of a trapping site which is attributable to the diffusion of moisture or H atoms from the interlayer insulating film into the tunneling oxide film can be suppressed, thereby improving the trap-up-rate and endurance characteristic and increasing the number of times of erasure/write of data to extend the operation life of the memory cell portion.
The trapping of moisture or H atoms diffused from the interlayer insulating film by the gate oxide film can be also suppressed so that the resistance against hot carriers of the transistor can be improved.
The above and other objects and features of the invention will be more apparent from the following description taken in conjunction with the accompanying drawings.